A plurality of transistors that have been produced on the same silicon chip have all been produced under exactly the same conditions and therefore have characteristics such as threshold voltage and mutual conductance that are essentially matched. As a result, a balanced-input circuit that uses transistors is ideal for detecting a microsignal, and components such as differential amplification circuits and differential sampling latch circuits are frequently used in the input stage of a signal detection circuit for detecting data of a received signal.
However, variation occurs in characteristics such as the threshold voltage or mutual conductance of actual transistors. These variations in characteristics arise from temperature differences within a chip or from various fabrication steps such as ion implantation, diffusion, or patterning that employs photoresist, or result from statistical variations.
When these variations in characteristics occur in a signal detection circuit, all of the variations are combined and appear as offset voltage. The minimum input difference in potential that can be detected by a signal detection circuit is determined by this offset voltage.
In wired communication in recent years, the amplitude of received signals has decreased markedly with the higher data transmission speeds, and there is a trend for the difference in potential of signals that are applied to signal detection circuits to further decrease as communication speeds increase.
As previously described, the input difference in potential that can be detected in a signal detection circuit is determined by the offset voltage, and the problem therefore arises that the false detection rate of data of low-amplitude high-speed received signals is exacerbated by the offset voltage.
The invention disclosed by Japanese Patent Laid-Open No. 2004-030797 is one known means of the related art for correcting the offset voltage of a signal detection circuit.
The signal detection circuit described in Japanese Patent Laid-Open No. 2004-030797 includes a training sequence (adjustment pattern) generation circuit for adjusting offset voltage whereby a data sequence generated in the training sequence generation circuit during the operation of system initialization is applied as input to a signal detection circuit, the data sequence applied as input to the signal detection circuit is compared with the data sequence detected in the signal detection circuit in bit units, and the offset voltage of the signal detection circuit then adjusted based on the detection results of bit errors.
However, the configuration described in Japanese Patent Laid-Open No. 2004-030797 requires a training sequence (adjustment pattern) generation circuit that is dedicated to the correction of the offset voltage of the signal detection circuit. There is a further problem that the self-test for correcting the offset voltage of the above-described signal detection circuit is implemented during operations for system initialization, and correction therefore cannot be realized for fluctuations of the offset voltage generated by such factors as the temperature fluctuations during use of the system. One solution that can be considered for this problem is the implementation of self-testing periodically or according to necessity after the start of data communication. However, the implementation of self-testing prevents the reception of signals in the signal detection circuit and the inability to send information results in a decrease of the effective communication speed.